A semiconductor memory device typically has multiple internal signal lines for storing data in memory cells and outputting the data. Among the signal lines, a pair of data input and output lines is at the same voltage in a precharged state and at a complementary voltage during writing and reading operation. In writing and reading successive data, the data is written or output depending on a burst length. In order to write or read subsequent data, the data input and output line pair should be equalized and precharged to the same voltage.
FIG. 1 illustrates an equalizing and precharging circuit for a typical semiconductor device. Referring to FIG. 1, an equalizing and precharging circuit 100 is composed of a first data line IO, a second data line /IO, a first equalizing transistor N1 connected between the data lines for equalizing the data lines in response to an enable signal EN, and second and third precharging transistors N2 and N3 for precharging the data lines to a certain voltage in response to the enable signal EN. The first, second and third transistors have body terminals connected to a ground voltage.
Operation of the equalizing and precharging circuit 100 of FIG. 1 will be described. In a precharged state of the semiconductor device, the enable signal EN becomes active. Accordingly, the equalizing transistor N1 and the precharging transistors N2 and N3 are turned on, precharging the data lines IO and /IO to a certain voltage, i.e., an internal power supply voltage IVC. In the writing and reading operation, the enable signal EN becomes inactive. This turns the equalizing transistor N1 and the precharging transistors N2 and N3 off, enabling a writing driver and a data sense amplifier (not shown) to supply a complementary voltage to each data line IO and /IO. In order to write and read subsequent data depending on a burst length, the data lines should be again equalized and precharged to the internal power supply voltage IVC.
In the equalizing and precharging circuit 100 as shown in FIG. 1, a voltage on the data line acting as a source of the precharging transistor N2 or N3 increases with the equalizing and precharging operation, thereby reducing Vgs of the precharging transistors. In addition, a threshold voltage Vth of the precharging transistors increases with an increasing source voltage due to a body effect (Vth∝√{square root over (Vbs)}) since the body regions of the precharging transistors N2 and N3 are fixed at the ground voltage. This threshold voltage increase degrades driving capability of the precharging transistors and the precharge speed of the data lines to the internal power supply voltage. Similarly, since Vgs of the equalizing transistor N1 decreases with an increasing voltage on the data line acting as the source and the body of the equalizing transistor N1 is fixed at the ground voltage, the threshold voltage Vth increases due to the body effect. This degrades the driving capability of the equalizing transistor and the equalizing speed of the data lines.
The above-described equalizing and precharging operation degrade the equalizing and precharging speed of the data input and output lines, such that the equalizing and precharging speed of the data input and output lines limits the operation frequency of a semiconductor device requiring high-speed writing and reading operations.